a Computer Architecture Reading Group @ KAIST

- Quick link: sigmp
- Contact us: root [_at_]

All slides attached in this homepage are only accessible in the KAIST network.

Date Presenter Title Venue Slide
09-04 Sunho Lee An Extremely Simple ORAM Protocol - Path ORAM JACM '18 PDF
07-10 Seonjin Na Griffin: Hardware-Software Support for Efficient Page Migration in Multi-GPU Systems HPCA '20 PDF
06-26 Soojin Hwang Leaking Information Through Cache LRU States HPCA '20 PDF
05-15 Seungbeom Choi MASR: A Modular Accelerator for Sparse RNNs PACT '19 PDF
04-03 Daehyen Baek SIGMA: A Sparse and Irregular GEMM Accelerator with Flexible Interconnects for DNN Training HPCA '20 PDF
03-06 Seonjin Na Efficient Metadata Management for Irregular Data Prefetching ISCA '19 PPTX
02-14 Soojin Hwang Applying Deep Learning to the Cache Replacement Problem MICRO '19 PPTX
01-17 Daehyen Baek Blasting Through The Front-End Bottleneck With Shotgun ASPLOS '18 PDF
Date Presenter Title Venue Slide
12-13 Jooun Park Simba: Scaling Deep-Learning Inference with Multi-Chip-Module-Based Architecture MICRO '19 PDF
11-15 Jeon Yoonjae Prefetched address translation ISCA '19 PPTX
11-08 Seonjin Na A Framework for Memory Oversubscription Management in Graphics Processing Units ASPLOS '19 PPTX
11-01 SooJin Hwang SecDir: A Secure Directory to Defeat Directory Side-Channel Attacks ISCA '19 PPTX
10-18 Daehyen Baek FPGA-Accelerated Cycle-Exact Scale-Out System Simulation in the Public Cloud ISCA '18 PDF
10-11 Jungi Jeong CoNDA: Efficient Cache Coherence Support for Near-Data Accelerators ISCA '19 PDF
10-04 Sukchul Cho The Accelerator Wall: Limits of Chip Specialization HPCA '19 PPTX
09-27 Joongun Park TVM: An Automated End-to-End Optimizing Compiler for Deep Learning OSDI '18 PDF
09-06 Seonjin Na Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs using Machine Learning HPCA '19 PDF
08-30 Soojin Hwang ROTE: Rollback Protection for Trusted Execution USENIX Security '17 PPTX
08-30 Taeksoo Kim Translation Ranger: Operating System Support for Contiguity-Aware TLBs ISCA '19 PPTX
08-23 Taekyung Heo PageSeer: Using Page Walks to Trigger Page Swaps in Hybrid Memory Systems HPCA '19 PPTX
08-09 Daehyen Baek OuterSPACE : An Outer Product based Sparse Matrix Multiplication Accelerator HPCA '18 PPTX
08-02 Taehoon Kim Janus: Optimizing Memory and Storage Support for Non-Volatile Memory Systems ISCA '19 PPTX
07-25 Hyunwoo Jung GeneSys: Enabling Continuous Learning through Neural Network Evolution in Hardware MICRO '18 PPTX
07-05 Sukchul Cho Accelerating Distributed Reinforcement Learning with In-Switch Computing ISCA '19 PPTX
05-24 Seungbeom Choi A Configurable Cloud-Scale DNN Processor for Real-Time AI ISCA '18 PDF
05-10 Joongun Park PROMISE: An End-to-End Design of a Programmable Mixed-Signal Accelerator for Machine-Learning Algorithms ISCA '18 PDF
05-03 Taehoon Kim Enabling Transparent Memory-Compression for Commodity Memory Systems HPCA '19 PPTX
04-26 Jungi Jeong DHTM: Durable Hardware Transactional Memory ISCA '18 PDF
04-12 Taekyung Heo Compress Objects, Not Cache Lines: An Object-Based Compressed Memory Hierarchy ASPLOS '19 PDF
04-12 Changhyun Park Rethinking the Memory Hierarchy for Modern Languages MICRO '18 PDF
04-05 Insu Jang Heterogeneous Isolated Execution for Commodity GPUs ASPLOS '19
03-29 Seungbeom Choi An Architectural Framework for Accelerating Dynamic Parallel Algorithms on Reconfigurable Hardware MICRO '18 PDF
03-15 Seunghyo Kang Persistence Parallelism Optimization: A Holistic Approach from Memory Bus to RDMA Network MICRO '18 PPTX
02-22 Seonjin Na RegMutex: Inter-Warp GPU Register Time-Sharing ISCA '18 PDF
01-25 Joongun Park InvisiSpec: Making Speculative Execution Invisible in the Cache Hierarchy MICRO '18 PDF
01-04 Taehoon Kim Reducing DRAM Latency via Charge-Level-Aware Look-Ahead Partial Restoration MICRO '18 PDF
Date Presenter Title Venue Slide
12-28 Seonyoung Lee Combining HW/SW Mechanisms to Improve NUMA Performance of Multi-GPU Systems MICRO '18 PPTX
12-21 Ganguk Lee Architectural Support for Efficient Large-Scale Automata Processing MICRO '18 PPTX
11-16 Taekyung Heo Compresso: Pragmatic Main Memory Compression MICRO '18 PDF
11-09 Wonsang Kwak FlashAbacus: A Self-Governing Flash-Based Accelerator for Low-Power Systems EuroSys'18 PDF
10-05 Seungbeom Choi Computation Reuse in DNNs by Exploiting Input Similarity ISCA '18 PDF
09-28 Chang Hyun Park SEESAW: Using Superpages to Improve VIPT Caches ISCA '18 PDF
09-07 Seonjin Na Scheduling Page Table Walks for Irregular GPU Application ISCA '18 PDF
08-31 Seunghyo Kang Rethinking Belady's Algorithm to Accommodate Prefetching ISCA '18 PPT
08-03 Joongun Park A Hardware Accelerator for Tracing Garbage Collection ISCA '18 PPT
07-20 Taehoon Kim ACCORD: Enabling Associativity for Gigascale DRAM Caches by Coordinating Way-Install and Way-Prediction ISCA '18 PDF
07-13 Seonyoung Lee Mosaic: A GPU Memory Manager with Application-Transparent Support for Multiple Page Sizes MICRO '17 PPT
06-29 Ganguk Lee Darwin: A Genomic Co-processor Provides up to 15,000X acceleration on long read assembly ASPLOS '18 PDF
06-08 Wonsang Kwak PipeLayer: A Pipelined ReRAM-Based Accelerator for Deep Learning HPCA '17 PDF
05-28 Chang Hyun Park Avoiding TLB Shootdowns Through Self-Invalidating TLB Entries PACT '17 PPT
05-17 Jungi Jeong An Event-Triggered Programmable Prefetcher for Irregular Workloads ASPLOS '18 PPT PDF
04-27 Seungbeom Choi LogCA: A High-Level Performance Model for Hardware Accelerators ISCA '17 PDF
03-30 Seunghyo Kang Transparent Hardware Management of Stacked DRAM as Part of Memory MICRO '14 PPT
03-23 Seonjin Na Access Pattern-Aware Cache Management for Improving Data Utilization in GPU ISCA '17 PDF
03-16 Joongun Park How secure is your cache against side-channel attacks? MICRO '17 PDF
03-02 Taehoon Kim PageForge: A Near-Memory Content- Aware Page-Merging Architecture MICRO '17 PDF
01-26 Seonyoung Lee Fine-Grained DRAM: Energy Efficient DRAM for Extreme Bandwidth Systems MICRO '17 PPT
01-19 Ganguk Lee Perceptron Learning for Reuse Prediction MICRO '16 PPT
01-12 Wonsang Kwak PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory ISCA '16 PPT
Date Presenter Title Venue Slide
12-08 Jaewook Woo SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks ISCA '17 PPT
12-01 Jungi Jeong Efficient Support of Position Independence on Non-Volatile Memory MICRO '17 PPT
11-17 Taekyung Heo Hardware Supported Persistent Object Address Translation MICRO '17 PDF
11-10 Changhyun Park CSALT: context switch aware large TLB MICRO '17 PPT
11-03 Seungbeom Choi CNVLUTIN : Ineffectual-neuron-free DNN Computing ISCA '16 PPT
10-13 Bokyeong Kim HeteroOS - OS Design for Heterogeneous Memory Management in Datacenter ISCA '17 PDF
09-15 Ganguk Lee SHiP: Signature-based Hit Predictor for high performance caching MICRO '11 PPT
08-25 Jungi Jeong Hiding the Long Latency of Persist Barriers Using Speculative Execution ISCA '17 PPT
08-18 Wonsang Kwak Kill the Program Counter: Reconstructing Program Behavior in the Processor Cache Hierarchy ASPLOS '17 PPT
08-04 Taekyung Heo Jenga: Sotware-Defined Cache Hierarchies ISCA '17 PDF
07-28 Changhyun Park The Mondrian Data Engine ISCA '17 PPT
07-21 Seungbeom Choi In-Datacenter Performance Analysis of a Tensor Processing Unit ISCA '17 PPT
07-14 Insu Jang Understanding The Security of Discrete GPUs GPGPU '17 PPT
06-30 Seonjin Na Warped-Slicer: Efficient Intra-SM Slicing through Dynamic Resource Partitioning for GPU Multiprogramming ISCA '16 PPT
06-16 Seonyoung Lee SoftMC: A Flexible and Practical Open-Source Infrastructure for Enabling Experimental DRAM Studies HPCA '17 PPT
06-09 Joongun Park Back to the Future: Leveraging Belady's Algorithm for Improved Cache Replacement ISCA '16 PDF
05-26 Jaeseong Im Efficient data supply for hardware accelerators with prefetching and access/execute decoupling Micro '16 PPT
05-12 Bokyeong Kim Thermostat: Application-transparent Page Management for Two-tiered Main Memory ASPLOS '17 PDF
04-28 Taehoon Kim Secure Dynamic Memory Scheduling Against Timing Channel Attacks HPCA '17 PPT
04-21 Ganguk Lee From High-Level Deep Neural Models to FPGAs MICRO '16 PPT
04-14 Taekyung Heo SWAP: Effective Fine-Grain Management of Shared Last-Level Caches with Minimum Hardware Support HPCA '17 PPT
04-07 Jungi Jeong NVMMU: A Non-Volatile Memory Management Unit for Heterogeneous GPU-SSD Architectures PACT '15 PPT
03-31 Changhyun Park Supporting Address Translation for Accelerator-Centric Architectures HPCA '17 PPT
03-24 Jonguk Kim APRES: Improving Cache Efficiency by Exploiting Load Characteristics on GPUs ISCA '16 PPT
02-24 Seungbeom Choi Warped-Preexecution: A GPU Pre-execution Approach for Improving Latency Hiding HPCA '16 PPT
02-17 Insu Jang Refree: A Refresh-Free Hybrid DRAM/PCM Main Memory System IPDPS '16 PPT
02-3 Seonjin Na Equalizer: Dynamic Tuning of GPU Resources for Efficient Execution MICRO '14 PPT
01-20 Sanghoon Cha CANDY: Enabling Coherent DRAM Caches for Multi-node Systems MICRO '16 PPT
01-06 Seonyoung Lee C3D: Mitigating the NUMA Bottleneck via Coherent DRAM Caches MICRO '16 PPT
Date Presenter Title Venue Slide
12-23 Jaeseong Im Jump Over ASLR: Attacking Branch Predictors to Bypass ASLR MICRO '16 PPT
12-07 Changdae Kim Treadmill Attributing the Source of Tail Latency through Precise Load Testing and Statistical Inference* ISCA '16 PPT
12-02 Bokyeong Kim Reactive NUCA: Near-Optimal Block Placement and Replication in Distributed Caches ISCA '09 PPT
11-25 Taehoon Kim Improving Energy Efficiency of DRAM by Exploiting Half Page Row Access MICRO '16 PPT
11-11 Ganguk Lee Path Confidence based Lookahead Prefetching MICRO '16 PPT
10-28 Taekyung Heo Zorua: A Holistic Approach to Resource Virtualization in GPUs MICRO '16 PPT
10-07 Wonik Seo Asymmetry-Aware Work-Stealing Runtimes ISCA '16 PPT
10-05 Taesoo Lee LASER: Light, Accurate Sharing dEtection and Repair* HPCA '16 PPT
09-30 Jungi Jeong LAP:Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches ISCA '16 PDF
08-31 Changdae Kim Modeling Cache Performance Beyond LRU HPCA '16 PPT
08-26 Jonguk Kim LaPerm: Locality Aware Scheduler for Dynamic Parallelism on GPUs ISCA '16 PPT
08-12 Seungbeom Choi EIE: Efficient Inference Engine on Compressed Deep Neural Network ISCA '16 PPT
08-05 Seonjin Na Data Cache Prefetching Using a Global History Buffer HPCA '04 PPT
08-03 Insu Jang CAMEO:A Two-Level Memory Organization with Capacity of Main Memory and Flexibility of Hardware-Managed Cache MICRO '14 PPT
07-29 Sanghoon Cha Low-Cost Inter-Linked Subarrays (LISA): Enabling Fast Inter-Subarray Data Movement in DRAM HPCA'16 PPT
07-22 Seonyoung Lee ChargeCache: Reducing DRAM Latency by Exploiting Row Access Locality HPCA'16 PPT
07-15 Jaeseong Im Efficiently Scaling Out-of-Order Cores for Simultaneous Multithreading ISCA '16 PPT Comments
07-08 Bokyeong Kim Agile Paging: Exceeding the Best of Nested and Shadow Paging ISCA '16 PPT
07-01 Taehoon Kim MITTS:Memory Inter-arrival Time Traffic Shaping ISCA '16 PPT
06-10 Ganguk Lee Efficiently Prefetching Complex Address Patterns MICRO '15 PDF
06-03 Taesoo Lee Efficient GPU Hardware Transactional Memory through Early Conflict Resolution HPCA '16 PPT
05-20 Seungheun Jeon Silent Shredder: Zero-Cost Shredding for Secure Non-Volatile Main Memory Controllers ASPLOS '16 PPT
04-27 Seonyoung Lee DUANG: Lightweight Page Migration in Asymmetric Memory Systems* HPCA '16 PPT
04-15 Taekyung Heo Neural Acceleration for GPU Throughput Processors MICRO '15 PDF
04-08 Wonik Seo Microarchitectural Implications of Event-driven Server-side Web Applications MICRO '15 PDF
04-06 Taesoo Lee Minimal Disturbance Placement and Promotion* HPCA '16 PPT
04-01 Jungi Jeong Atomic Persistence for SCM with a Non-intrusive Backend Controller HPCA '16 PPT
03-25 Chang Hyun Park Energy-Efficient Address Translation HPCA '16 PPT
03-18 Changdae Kim DynaMOS: Dynamic Schedule Migration for Heterogeneous Cores MICRO '15 PPT
03-04 Jonguk Kim WarpPool: sharing Requests with Inter-Warp coalescing for Throughput Processors MICRO '15 PPT
02-12 Seonyoung Lee ThyNVM: Enabling Software-Transparent Crash Consistency in Persistent Memory Systems MICRO '15 PPT
01-29 Taehoon Kim Decoupled Direct Memory Access: Isolating CPU and IO Traffic by Leveraging a Dual-Data-Port DRAM PACT '15 PPT
01-22 Ganguk Lee The Application Slowdown Model: Quantifying and Controlling the Imact of Inter-Application Interference at Shared Caches and Main Memory MICRO '15 PPT
01-15 Bokyeong Kim Large Pages and Lightweight Memory Management in Virtualized Environments: Can You Have it Both Ways? MICRO '15 PDF
* Papers presented in SIGOPS but relevant to SigARCH nonetheless.

Date Presenter Title Venue Slide
12-18 Seungheun Jeon Gather-Scatter DRAM: In-DRAM Address Translation to Improve the Spatial Locality of Non-unit Strided Accesses MICRO '15 PPT PPT2
11-20 Wonik Seo Domain Knowledge Based Energy Management in Handhelds HPCA '15 PPT
11-13 Jungi Jeong FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems MICRO '14 PPT
11-06 Chang Hyun Park Stash: Have your scratchpad and cache it too ISCA '15 PDF
10-30 Changdae Kim A Fully Associative, Tagless DRAM Cache ISCA '15 PPT
10-23 Sanghoon Cha The Load Slice Core Microarchitecture ISCA '15 PDF
10-08 Seonyoung Lee BEAR: Techniques for Mitigating Bandwidth Bloat in Gigascale DRAM Caches ISCA '15 PPT
10-02 Taehoon Kim Alloy: Parallel-Serial Memory Channel Architecture for Single-Chip Heterogeneous Processor System HPCA '15 PPT
09-24 Bokyeong Kim Prediction-based superpage-friendly TLB designs HPCA '15 PPT
09-11 Taesoo Lee Talus: A Simple Way to Remove Cliffs in Cache Performance HPCA '15 PPT
08-28 Seungheun Jeon Parallelism Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems ISCA '08 PPT
08-07 Jongyul Kim A Case for Core-assisted Bottleneck Acceleration in GPUs: Enabling Flexible Data Compression with Assist Warps ISCA '15 PPT
07-31 Wonik Seo Accelerating Asynchronous Programs through Event Sneak Peak ISCA '15 PPT
07-24 Taekyung Heo Protecting Data on Smartphones and Tablets from Memory Attacks ASPLOS '15
07-17 Jungi Jeong A Scalable Processing in Memory Accelerator for Parallel Graph Processing ISCA '15 PDF
07-16 Seikwon Kim Base-Delta-Immediate Compression: Practical Data Compression for On-Chip Caches* PACT '12 PPT
07-10 Chang Hyun Park Architectural Support for Dynamic Linking ASPLOS '15 PPT
07-09 Taehoon Kim DEUCE: Write-Efficient Encryption for Non-Volatile Memories* ASPLOS '15 PPT
07-03 Daegil Im Understanding Idle Behavior and Power Gating Mechanisms in the Context of Modern Benchmarks on CPU-GPU Integrated Systems HPCA '15 PPT
07-02 Seonyoung Lee Unison Cache: A Scalable and Effective Die-Stacked DRAM Cache* MICRO '14 PPT
06-05 Changdae Kim SMiTe: Precise QoS Prediction on Real-System SMT Processors to Improve Utilization in Warehouse Scale Computers MICRO '14 PPT
05-29 Sanghoon Cha Exploiting Compressed Block Size as an Indicator of Future Reuse HPCA '15 PDF
05-08 Seonyoung Lee DaDianNao: A Machine-Learning Supercomputer MICRO '14 PPT
05-01 Taehoon Kim Adaptive-Latency DRAM:Optimizing DRAM Timing for the Common-Case HPCA '15 PPT
04-17 Bokyeong Kim (NDA) Near-DRAM Acceleration Architecture Leveraging Commodity DRAM Devices and Standard Memory Modules HPCA '15 PPT
04-10 Jaeseong Im An opportunistic Prediction-based Thread Scheduling to Maximize Throughput/Watt in AMPs PACT '13 PPT
04-03 Junghoon Lee Page Placement Strategies for GPUs within Heterogeneous Memory Systems ASPLOS '15
03-27 Jongyul Kim COMP: Compiler Optimizations for Manycore Processors MICRO '14 PDF
03-13 Taekyung Heo ArchRanker A Ranking Approach to Design Space Exploration ISCA '14 PPT
03-06 Chang Hyun Park Improving the Energy Efficiency of Big Cores ISCA '14 PDF
02-27 Daegil Im Cooperative Cache Scrubbing PACT '14 PPT
02-13 Changdae Kim System-Level Performance Metrics for Multiprogram Workloads
Fairness metrics for multi-threaded processors
Arch Letter '11
02-06 Sanghoon Cha The Dirty-Block Index ISCA '14 PPT
01-23 Ganguk Lee RowClone: Fast and Energy-Efficient In-DRAM Bulk Data Copy and Initialization MICRO '13 PPT
01-16 Jungim Choi Futility Scaling: High-Associativity Cache Partitioning MICRO '14 PPT
* Papers presented in SIGOPS but relevant to SigARCH nonetheless.

Date Presenter Title Venue Slide
12-19 Seonyoung Lee Reducing Memory Reference Energy with Opportunistic Virtual Caching ISCA '12 PPT
11-21 Taehoon Kim Simple but Effective Heterogeneous Main Memory with On-Chip Memory Controller Support SC '10 PPT
11-14 Bokyeong Kim STM: Cloning the Spatial and Temporal Memory Access Behavior HPCA '14
10-10 Wonik Seo Imbalanced Cache Partitioning for Balanced Data-Parallel Programs MICRO '13 PDF
09-26 Junghoon Lee XStream: Cross-core Spatial Streaming based MLC Prefetchers for Parallel Applications in CMPs PACT '14
09-19 Chang Hyun Park The Direct-to-Data (D2D) Cache: Navigating the Cache Hierarchy with a Single Lookup ISCA '14 PPT
09-12 Seonyoung Lee MLP-Aware Dynamic Instruction Window Resizing for Adaptively Exploiting Both ILP and MLP MICRO '13 PPT
09-05 Jungi Jeong WebCore: Architectural Support for Mobile Web Browsing ISCA '14 PPT
08-29 Changdae Kim Flicker: A Dynamically Adaptive Architecture for Power Limited Multicore Systems ISCA '13 PPT
08-22 Sanghoon Cha Half-DRAM: A High-bandwidth and Low-Power DRAM Architecture from the Rethinking of Fine-grained Activation ISCA '14
08-08 Jeongseob Ahn Thin Servers with Smart Pipes: Designing SoC Accelerators for Memcached ISCA '13 PPT
08-01 Jeongim Choi Improving DRAM Performance by Parallelizing Refreshes with Accesses HPCA '14 LINK
07-25 Jongyul Kim Stash Directory: A Scalable Directory for Many-Core Coherence HPCA '14
07-18 Jaeung Han Towards Energy Proportionality for Large-Scale Latency-Critical Workloads ISCA '14
07-11 Wonjun Song Stealing Webpages Rendered on Your Browser By exploring GPU Vulnerabilities S&P '14 LINK
07-04 Taehoon Kim Die-Stacked DRAM Caches for Servers ISCA '13 PPT, Link
06-20 Bokyeong Kim Meet the Walkers: Accelerating Index Traversals for In-Memory Databases MICRO '13 Link
05-30 Wonik Seo Trace Based Phase Prediction For Tightly-Coupled Heterogeneous Cores MICRO '13 PPT
05-23 Junghoon Lee A Case for MLP-Aware Cache Replacement ISCA '06
05-16 Chang Hyun Park The Sharing Architecture:Sub-Core Configurability for IaaS Clouds ASPLOS '14 Link
05-02 Seonyoung Lee Quasar: Resource-Efficient and QoS-Aware Cluster Management ASPLOS '14 PPT
04-18 Jungi Jeong Scale-Out NUMA ASPLOS '14 PPT
03-28 Changdae Kim Multi-Grain Coherence Directory MICRO '13 PPT
03-21 Gwangsun Kim NUAT: A Non-Uniform Access Time Memory Controller HPCA '14
03-14 Sanghoon Cha Ubik: Efficient Cache Sharing with Strict QoS for Latency-Critical Workloads ASPLOS '14
03-07 Jeongseob Ahn Increasing TLB Reach by Exploiting Clustering in Page Translations HPCA '14 PPT
02-14 Taehoon Kim CPU Transparent Protection of OS Kernel and Hypervisor Integrity with Programmable DRAM ISCA '13 PPT
01-24 Jaeung Han Heterogeneous System Coherence for Integrated CPU-GPU Systems MICRO '13 Link
01-17 Wonjun Song Efficient Timing Channel Protection for On-Chip Networks NOCS '12 PPT
01-03 Jongyul Kim Handling branches in TLS systems with Multi-Path Execution HPCA '10 PPT

Date Presenter Title Venue Slide
12-27 Jungi Jeong Whare-Map: Heterogeneity in Homogeneous Warehouse-Scale Computers ISCA '13 PPT
12-06 Hyungho Choi Resilient Die-stacked DRAM Caches ISCA '13 PPT
11-29 Wonik Seo Illusionist: Transforming Lightweight Cores into Aggressive Cores on Demand HPCA '13 PPT
11-15 Junghoon Lee Secure I/O Device Sharing among Virtual Machines on Multiple Hosts ISCA '13 PDF
11-08 Chang Hyun Park Efficient Virtual Memory for Big Memory Servers ISCA '13 PPT
11-01 Seonyoung Lee LINQits: Big Data on Little Clients ISCA '13 PPT
10-18 Hanjoon Kim Scale-out Processors ISCA '12
10-11 Bokyeong Kim Navigating Big Data with High-Throughput, Energy-Efficient Data Partitioning ISCA '13 PPT
10-04 Gwangsun Kim Improving Memory Scheduling via Processor-Side Load Criticality Information ISCA '13
09-27 Sanghoon Cha Improving Virtualization in the Presence of Software Managed Translation Look-aside Buffers ISCA '13
09-13 Changdae Kim Agile, Efficient Virtualization Power Management with Low-latency Server Power States ISCA '13 PPT
08-30 Gwangsun Kim Memory-centric System Interconnect Design with Hybrid Memory Cubes PACT '13
08-23 Jeongseob Ahn Fairness via Source Throttling: A Configurable and High-Performance Fairness Substrate for Multi-Core Memory Systems ASPLOS '10 Link
08-16 Wonik Seo Parallelism-Aware Batch Scheduling: Enhancing both Performance and Fairness of Shared DRAM Systems ISCA '08 Link
08-09 Jaeung Han Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors MICRO '07 Link